1. Field of the Invention
The present invention relates to semiconductor logic circuits, and specifically to a semiconductor logic circuit including a bipolar transistor and a field effect transistor of complimentary type. The present invention relates more specifically to a semiconductor logic circuit capable of stably reducing the logic amplitude of an output signal.
2. Description of the Background Art
A semiconductor logic circuit is often implemented using only complimentary type field effect transistors (hereinafter simply referred to as CMOS transistors) in conventional circuit devices. This is because steady-state current flows through a CMOS transistor only in its switching operation, and the current consumption is reduced compared to a semiconductor logic circuit using a bipolar transistor as an element. In addition, a MOS transistor (insulating gate type field effect transistor) occupies a smaller area than a bipolar transistor, and, therefore, semiconductor logic circuits have higher component densities and integrations year by year.
However, the loads which some logic circuits need to drive increase in accordance with the higher integration. In the case of a circuit intended to supply clock signals to a number of logic circuits such as a clock driver, an excessively large load rounds its output waveform, resulting in increase of time required for signal transmission. In order to reduce the time for signal transmission by driving this large output load at a high speed, a composite circuit provided with a bipolar transistor having a high current driving capability has been used in the output stage of a large load (output load) logic circuit in recent years. A configuration of such a composite circuit will be described in the following.
FIG. 18 is a diagram showing a conventional semiconductor logic circuit, illustrating an inverter gate for inverting an input signal. In FIG. 18, the inverter gate includes a p channel MOS transistor 1 and an n channel MOS transistor 2 connected in a complimentary fashion between a first power supply potential Vdd and second power supply potential Vss. The gates of MOS transistors 1 and 2 are connected to an input signal line 11. The drains of MOS transistors 1 and 2 are connected to an output signal line 12. The inverter gale shown FIG. 18 is a CMOS inverter circuit which does not include a bipolar transistor, but is illustrated for the purpose of comparison to other composite circuits. The operation will be briefly described.
With an input potential Vin applied on input signal line 11 being low (normally it is at the level of low power supply potential Vss, and is often assumed to be at the level of ground potential GND), p channel transistor 1 is conductive, and n channel MOS transistor 2 is turned off. Output signal line 12 is charged from first power supply potential Vdd through p channel MOS transistor 1, and the output potential Vout of output signal line 12 is pulled up to a high level. The output potential Vout is usually at the level of first power supply potential Vdd.
With the input potential Vin being high, p channel MOS transistor is turned off, and n channel MOS transistor 2 is conductive so that output signal line 12 is discharged to second power supply potential Vss through the conducting n channel MOS transistor. Thus, the output potential Vout decreases to a low potential (the level potential Vss). In other words, the output potential Vout becomes a potential in a logic inverted to the input potential Vin.
FIG. 19 is a diagram showing a configuration on a conventional semiconductor logic circuit called a BiNMOS gate. In FIG. 19, the BiNMOS gate includes a p channel MOS transistor 1 and an n channel MOS transistor 2 connected in a complimentary fashion between first power supply potential Vdd and second power supply potential Vss, a resistor 4 connected between one conduction terminal (drain) of p channel MOS transistor 1 and output signal lines 12, and npn bipolar transistor 3 having its collector connected to first power supply potential Vdd, its emitter connected to output signal line 12, and its base connected to the one conduction terminal (drain) of p channel MOS transistor 1. The BiNMOS gate charges output signal line 12 through bipolar transistor 3, and discharges output signal line 12 through n channel MOS transistor 2. The operation thereof will be described.
With an input potential Vin on input signal line 11 being low, p channel MOS transistor 1 is conductive, while n channel MOS transistor 2 is turned off. A base current is supplied to the base of npn bipolar transistor 3 through the conductive p channel MOS transistor 1. Also at that time, current flows to resistor 4 through p channel MOS transistor 1, and the potential difference across resistor 4 provides a base-emitter voltage (about 0.5 V) necessary for turning on npn bipolar transistor 3. When the base-emitter region of bipolar transistor 3 is biased in the forward direction due to the potential difference at resistor 4, bipolar transistor 3 conducts. Npn bipolar transistor 3 supplies an emitter current as large as the current amplification factor times (usually about 100 times) the base current. This pulls up the output potential Vout at a higher speed as compared to the configuration of the CMOS inverter gate shown in FIG. 18.
The high potential of the output potential Vout is ultimately charged to the level of the power supply potential Vdd through p channel MOS transistor 1 and resistor 4.
With the input potential Vin being high, p channel MOS transistor 1 is turned off, and bipolar transistor 3 is also turned off, while n channel MOS transistor 2 conducts. Output signal line 12, as is the case with the CMOS inverter gate shown in FIG. 18, is discharged to the level of the second power supply potential Vss through n channel MOS transistor 2.
FIG. 20 is a diagram showing another configuration of a conventional semiconductor logic circuit. The semiconductor logic circuit shown in FIG. 20 includes, in addition to the configuration shown in FIG. 19, an n channel MOS transistor 5 connected between the base of npn bipolar transistor 3 and the second power supply potential Vss, a resistor 6 connected between n channel MOS transistor 2 and the second power supply potential Vss, and an npn bipolar transistor 7 connected between output signal line 12 and the second power supply potential Vss. The input potential Vin is applied to the gate of n channel MOS transistor 5. Npn bipolar transistor 7 has its collector connected to output signal line 12, its emitter connected to the second power supply potential Vss, and its base connected to the connection node of MOS transistor 2 and resistor 6. Resistor 6 is provided for applying the base-emitter voltage of npn bipolar transistor 7.
The semiconductor logic circuit shown in FIG. 20 charges/discharges through npn bipolar transistors 3 and 7, and is generally referred to as a BiCMOS gate. Its operation will be described in the following.
With the input potential Vin being low, p channel MOS transistor 1 is made conductive, while n channel MOS transistors 2 and 5 are turned off. In this case, as in the case with the BiNMOS gate shown in FIG. 19, a base current is supplied to the base of npn bipolar transistor 3 through MOS transistor 1, and bipolar transistor 3 having its base-emitter region forward-biased by resistor 4 conducts. Thus, output signal line 12 is charged at a high speed through bipolar transistor 3.
With the input potential Vin being high, n channel MOS transistors 2 and 5 are conductive and p channel MOS transistors 1 is turned off. In this case, the base current is supplied to the base of npn bipolar transistor 7 through output signal line 12, and bipolar transistor 7 has its base-emitter region forward-biased by resistor 6 and conducts. Thus, output signal line 12 is discharged at a high speed by the collector current of bipolar transistor 7. In the case of the BiCMOS gate shown in FIG. 20, the output potential Vout is pulled up at a higher speed compared to the BiNMOS gate shown in FIG. 19 accordingly.
When the output potential Vout is decreased, npn bipolar transistor 3 must be turned off at a high speed in order to cut off the charging of output signal 12 by npn bipolar transistor 3. N channel MOS transistor 5 is provided for this purpose. More specifically, n channel MOS transistor 5 is made conductive when the input voltage Vin changes its level from low to high, and extracts the base charges of npn bipolar transistor 3, turning off npn bipolar transistor 3 at a high speed.
FIG. 21 is a diagram showing another configuration of a conventional semiconductor logic circuit. In FIG. 21, the conventional semiconductor logic circuit includes p channel MOS transistors 1 and n channel MOS transistor 2 connected in a complimentary fashion between a first power supply potential Vdd and a second power supply potential Vss, a resistor 4 between p channel MOS transistor 1 and output signal line 11, a resistor 8 connected between output signal line 12 and n channel MOS transistor 2, an npn bipolar transistor 3 provided between the first power supply potential Vdd and output signal line 12, and a pnp bipolar transistor 9 connected between output signal line 12 and the second power supply potential Vss.
An input potential Vin is applied to the gates of p channel MOS transistor 1 and n channel MOS transistor 2. Npn bipolar transistor 3 has its collector connected to the first power supply potential Vdd, its emitter connected to output signal line 12, and its base connected to the common connection node of transistor 1 and resistor 4. Pnp bipolar transistor 9 has its emitter connected to output signal line 12, its collector connected to the second power supply potentials Vss, and its base connected to the common connection node of resistor 8 and transistor 2.
The semiconductor logic circuit shown in FIG. 21 charges output signal line 12 through npn bipolar transistor 3, while discharges output signal line 12 through pnp transistor 9 and is generally referred to as a CBiCMOS gate. Its operation will be described in the following.
When the input potential Vin is pulled down from high to low, p channel MOS transistor 1 is on while n channel MOS transistor 2 is turned off. Thus, a base current is supplied to npn bipolar transistor 3 through p channel MOS transistor 1, and output signal line 12 is charged at a high speed by the emitter current of this npn bipolar transistor 9, thus pulling up the output potential Vout at a high speed.
With the input potential Vin being pulled up from low to high, p channel MOS transistor 1 is turned off while n channel MOS transistor 2 is turned on. Thus, pnp bipolar transistor 9 has its base-emitter region forward-biased by resistor 8, and its base current is extracted at a high speed through n channel MOS transistor 2. This causes pnp bipolar transistor 9 to conduct at a high speed, pulling down the potential Vout of output signal line 12 at a high speed by its emitter current.
The configuration of the CBiCMOS gate shown in FIG. 21 permits reduction of elements as compared to the configuration of the BiCMOS gate shown in FIG. 20, because n channel MOS transistor 5 is not necessary.
As described above, a large load can be driven at a high speed by charging/discharging the out signal line 12, using a bipolar transistor having a large current driving capability. The following problem is however encountered when the output signal line is charged or discharged using the configurations of the composite circuits (a circuit including a bipolar transistor and an MOS transistor) shown in FIGS. 19 to 21.
When output signal line 12 is charged through a bipolar transistor, if the difference between the first power supply potential Vdd and the output potential Vout is smaller than a base-emitter voltage (Vbe: usually about 0.8 V) which is necessary for bipolar transistor 3 to conduct, the bipolar transistor is turned off. Therefore, if the output potential Vout is higher than Vdd minus Vbe, bipolar transistor 3 for charging the output signal line 12 attains the non-conduction state, output signal line 12 is charged by p channel MOS transistor 1 through a resistor (resistor 4 in FIGS. 19 to 21). The current driving capability of p channel MOS transistor 1 is smaller than that of bipolar transistor 3. The speed of pulling up of the output potential Vout rapidly decreases. Especially in the cases of the semiconductor logic circuits shown in FIGS. 20 and 21, in the potential amplitude of output signal line 12, in the upper side Vbe region (the region covering the first power supply potential Vdd to Vdd-Vbe) and the lower side Vbe (the region covering the second power supply potential Vss to Vss+Vbe), the bipolar transistor does not conduct. The state is shown in FIG. 22.
In FIG. 22, the lateral axis represents time, and longitudinal axis potential. Referring to FIG. 22, the region I represents the region of the upper Vbe, which is the region in which the bipolar transistor for charging output signal line 12 is turned off. The region II represents the region of the lower Vbe, which is the region in which the bipolar transistor for discharging output signal line 12 is turned off. As can be seen from FIG. 22, the presence of the region in which the bipolar transistor is turned off in each of the upper and lower sides of Vbe gives rise to a serious problem as the power supply voltage Vdd decreases.
The breakdown voltage of an MOS transistor decreases as a function of the down-scaling, and, therefore, a voltage applied across its source-drain region should be reduced. The power supply voltage Vdd should be reduced accordingly. In that case, the base-to-emitter voltage Vbe of a bipolar transistor is a constant value not subjected to the scaling, and, therefore, the magnitude of the above-stated 2.multidot.Vbe (the sum of the upper Vbe and lower Vbe) with respect to the power supply voltage becomes relatively large. The bipolar transistor is in the state of non-conduction in this region, and the superior quality (high speed operation property) of the BiCMOS gate or CBiCMOS gate to a CMOS gate is lost. More specifically, with low voltage supply, a BiCMOS circuit or a CBiCMOS circuit greatly deteriorates in high speed performance.
Two approaches have been suggested for such deterioration in high speed performance under a low supply voltage operating condition as in the following.
FIG. 23 illustrates the circuit configuration disclosed by C. L. Chen in the 1990 ISSCC (International Solid-State Circuits Conference) (see Technical Digest of 1990ISSCC, pp. 236-237).
The circuit shown in FIG. 23 includes an input stage 20 for receiving an input signal Vin and restricting its logic amplitude to output, a BiCMOS driver 21 for executing a prescribed logic operational processing on the signal from input stage 20, and an output stage 22 for receiving the output from BiCMOS driver 21 and applying a prescribed logic processing to the received output to output as an output potential Vout.
Input stage 20 includes a p channel MOS transistor 22 and an n channel MOS transistor 23 connected in a complimentary fashion for receiving the input potential Vin at their gates, a diode 21 connected between p channel MOS transistor 22 and a first power supply potential Vdd, and a diode 24 connected between n channel MOS transistor 23 and a second power supply potential Vss. Diodes 21 is connected in the forward direction between the first power supply potential Vdd and p channel MOS transistor 22. Diodes 24 is connected in the forward direction between n channel MOS transistor 23 and the second power supply potential Vss.
The substrate of p channel MOS transistor 22 is connected to the first power supply potential Vdd, while the substrate of n channel MOS transistor 23 is connected to the second power supply potential Vss. Input stage 20 is a CMOS inverter gate, and a logically inverted signal of the input potential Vin is output to a node N1. A high potential Vh appearing at node N1 is at the level of "Vdd-Vf", while a low potential V1 at node N1 is at the level of "Vss+Vf". Vf is the forward voltage of diodes 21 and 24, which is equal to the base-emitter voltage Vbe of the bipolar transistor if PN diodes are used for diodes 21 and 24.
Driver 21 at the intermediate stage is given its operation power supply potential by the power supply potentials Vdd and Vss, processes an output signal from the node N1 of input stage 20, and applies the processed signal to the node N2 of output stage 22. BiCMOS driver 21 includes a bipolar transistor and a CMOS transistor, and the logical amplitude of the input signal is given by "Vdd-Vf-Vf=Vdd-2.multidot.Vf." In this case, in BiCMOS driver 21, the high potential of the input signal is provided by Vdd-Vbe, while the low potential by Vbe (assuming that the second power supply potential Vss is ground potential GND), and therefore, the output potential is Vdd-Vbe at its high level and Vbe at its low level. In this case, the regions I and II shown in FIG. 22 are omitted from the logic amplitude, the bipolar transistor provided at the output of BiCMOS driver 21 conducts in the entire logic amplitude region, and the output is charged/discharged at a high speed.
Output stage 22 has a similar structure to input stage 20, and includes a diode 31, a p channel MOS transistor 32, an n channel MOS transistor 33 and a diode 34. The structure of output stage 22 renders the logic amplitude smaller than the power supply voltage Vdd by 2.multidot.Vf due to the presence of diodes 31 and 34.
More specifically, according to the structure shown in FIG. 23, the logic amplitude of an output signal from the BiCMOS circuit is matched to the level of the CMOS power supply voltage at output stage 22. The circuit configuration shown in FIG. 23 includes a circuit for level shift at the input and output of BiCMOS driver 21, and achieves the high speed operation by reducing its logic amplitude and constantly driving the bipolar transistors.
The circuit configuration of the level shift shown in FIG. 23, however, causes a backgate effect, because a diode is connected to the source of each MOS transistor in the CMOS gates of input stage 20 and output stage 22. In p channel MOS transistors 22 and 32, for example, the source potentials each become Vdd-Vf through diodes 21 and 31, while the substrate potentials each become Vdd. Thus, the substrate potentials of p channel MOS transistors 22 and 32 are biased relative to the sources by the amount of Vf, lowering the threshold voltages. Similarly in n channel MOS transistors 23 and 33, the difference between the system potential and substrate potential is provided by the amount of the forward voltage Vf of diodes 24 and 34, thus similarly increasing the threshold voltage. Current flowing through the MOS transistors decreases, and signal delay time tremendously increases as a result because a long period of time is required for charging/discharging nodes N1 and N3.
In the CMOS gate (output stage 22 and input-stage 20), in its steady state, either p channel MOS transistor (22 or 32) or n channel MOS transistor (23 or 33) is turned off, and no current path is therefore formed from the first power supply potential Vdd to the second power supply potential Vss. Current does not flow through diodes 21, 24 or diodes 31, 34 in the steady state, and, therefore, shift of the forward voltage Vf cannot be ensured.
Especially in output stage 22 in its steady state, the gate-source voltage of p channel MOS transistor 32 or n channel MOS transistor 33 becomes 0 V, and current does not flow to diodes 31 and 34 as a result. This keeps the forward voltage drop function of the diode from being fully effected, and it is therefore difficult to stably maintain its logic amplitude at the Vdd-Vf level.
FIG. 24 shows the structure of a BiCMOS circuit suggested together with the circuit structure shown in FIG. 23. Although a structure of 2 input NAND gate is illustrated in the above-stated document, a structure of an inverter gate will be described herein for the purpose of simplification. In FIG. 24, the BiCMOS gate includes at its input portion a structure similar to input stage 20 shown in FIG. 23. More specifically, the gate includes a p channel MOS transistor 41 and an n channel MOS transistor 42 connected in a complementary fashion between nodes N10 and N11, a diode 45 connected between node N10 and a first power supply potential Vdd, and a diode 46 connected between node Nil and a second power supply potential Vss.
The BiCMOS gate further includes an n channel MOS transistor 47 having its one conduction terminal (drain) connected to output signal line 12, its gate connected to input signal lines 11 and its source connected to the base of an npn bipolar transistor 49; an n channel MOS transistor 48 having its one conduction terminal (drain) connected to the other conduction terminal (source) of n channel MOS transistor 47 and the base of npn bipolar transistor 49, its the other conduction terminal (source) connected to node N11, and its gate connected to one conduction terminal (drain) of p channel MOS transistor 41; npn bipolar transistor 49 having its collector connected to output signal line 12, its emitter connected to the second power supply potential Vss, and its base connected to the other conduction terminal (source) of n channel MOS transistor 47; an npn bipolar transistor 43 having its collector connected to node N10, its emitter connected to output signal line 12, and its base connected to one conduction terminal (drain) of p channel MOS transistor 41 and the gate of n channel MOS transistor 48; and a p channel MOS transistor 44 having its one conduction terminal connected to node N10, its gate connected to input signal line 11, and its other conduction terminal connected to output signal line 12.
Now, the operation of the BiCMOS gate shown in FIG. 24 will be described.
With the input potential Vin being high, p channel MOS transistors 41 and 44 are turned off, while n channel MOS transistors 42 and 47 are conducting. Bipolar transistor 43 has its base current extracted through transistor 42 and is turned off at a high speed. Bipolar transistor 49 is turned on at a high speed and thus pulls down the output potential Vout of output signal line 12 because the base current of transistor 49 is supplied from signal line 12 through the conducting MOS transistor 47, and its base-emitter region is biased by diode 46.
With the input potential Vin being low, MOS transistors 42 and 47 are turned off, while p channel MOS transistors 41 and 44 conduct. Thus, base current is supplied to the base of bipolar transistor 43, turning on bipolar transistor 43 and charging signal line 12 at a high speed.
At that time, MOS transistor 48 conducts as well and extracts the base charges of bipolar transistor 49 at a high speed, turning off bipolar transistor 49. Thus, the output potential Vout of output signal line 12 is charged at a high speed. The base potential of bipolar transistor 43 is pulled up to Vdd-Vf at the maximum, and, therefore, the output potential Vout on output signal line 12 will be Vdd-Vf-Vbe=Vdd-2.multidot.Vf=Vdd-2.multidot.Vbe only with the provision of bipolar transistor 43 due to its emitter follower operation.
P channel MOS transistor 44 is therefore provided and drives the output potential Vout on output signal line 12 to the level of the potential Vdd-Vf (=Vdd-Vbe) of node N10.
In the case of the structure shown in FIG. 17, bipolar transistor 43 will not further pull up the potential of output signal line 12 once the potential of output signal line 12 reaches the level of Vdd-2.multidot.Vbe, and therefore, p channel MOS transistor 44 is used for driving the output potential Vout from the potential Vdd-2.multidot.Vbe to Vdd-Vbe. This creates the region in which the bipolar transistor does not operate, and the high speed performance property is lost.
FIG. 25 illustrates the structure of the CBiCMOS gate presented together with the circuits shown in FIGS. 22 and 23. A structure of 2 input gate circuit is also shown in the previously-stated document, but a structure of an inverter gate is instead shown in FIG. 25 for the purpose of simplification. Referring to FIG. 25, the CBiCMOS gate circuit includes a p channel MOS transistor 51 and an n channel MOS transistor 52 connected in a complimentary manner between nodes N21 and N22, a p channel MOS transistor 53 placed between nodes N23 and N21, a diode 55 placed between a first power supply potential Vdd and node N23, an n channel MOS transistor 54 placed between nodes N22 and N24, and a diode 56 placed between node N24 and a second power supply potential Vss.
The gates of p channel MOS transistor 51 and n channel MOS transistor 52 are provided with an input potential Vin. P channel MOS transistor 53 and n channel MOS transistor 54 have their gates connected to output signal line 12. Diodes 55 supplies a potential Vdd-Vf to node N23. Diode 56 supplies a potential Vss+Vf (=Vf) to node N24.
The CBiCMOS gate circuit further includes a pnp bipolar transistor 57 having its emitter connected to the first power supply potential Vdd, its collector connected to output signal line 12, and its base connected to node N21, and an npn bipolar transistor 58 having its collector connected to output signal lines 12, its emitter connected to the second power supply potential Vss, and its base connected to node N22. The operation will be briefly described.
With the input potential Vin being low, p channel MOS transistor 51 conducts, while n channel MOS transistor 52 is turned off. Thus, base charges are extracted from the base of pnp bipolar transistor 52, output signal line 12 is charged at a high speed through pnp bipolar transistor 52, pulling up the output potential Vout. The pull up potential is applied to the gates of n channel MOS transistor 54 and p channel MOS transistor 53, thus turning off p channel MOS transistor 53, and turning on n channel MOS transistor 54. Consequently, bipolar transistor 58 has its base charges extracted through transistor 54, and is turned off at a high speed, whereby output signal line 12 is charged through bipolar transistor 57.
With the input potential Vin being high, p channel MOS transistor 51 is turned off, while n channel MOS transistor 52 conducts. Thus, base current is supplied to the base of bipolar transistor 58, bipolar transistor 58 conducts, the charges are extracted from output signal line 12 at a high speed, and the output potential Vout is pulled down. As the potential Vout of output signal line 12 decreases, p channel MOS transistor 53 conducts, and base current is supplied to bipolar transistor 57, turning off bipolar transistor 57 at a high speed. Thus, output signal line 12 is charged at a high speed through bipolar transistor 58, and the output potential Vout decreases.
In the structure of the CBiCMOS gate circuit shown in FIG. 25, the emitter potential of pnp bipolar transistor 57 is offset by the amount of potential Vbe+the potential of node N23, while the emitter potential of npn bipolar transistor 58 is offset by the sum of Vbe and the potential of node N24. In the circuit structure shown in FIG. 25, reduction of the potential Vbe by bipolar transistors 57 and 58 permits the output potential Vout to be the potential of node N23 or N24.
However, in the case of structure of the CBiCMOS gate circuit shown in FIG. 25, bipolar transistors 57 and 58 for output are used in the emitter ground configuration. The collector-base junction of a bipolar transistor does not possess a potential clamping capability unlike the base-emitter junction. Therefore, the output potential Vout is not always offset by the amount of the base-emitter voltage Vbe from the respective power supply potentials Vdd and Vss in the steady state (the state in which the output potential Vout is stable).
In the case of circuit structures shown in FIGS. 24 and 25, as is the case with the circuit structure shown in FIG. 23, the source of MOS transistor is connected to a diode which is connected to the power supply potential Vdd or Vss, and the backgate effect prevails due to this structure, decreasing the amount of current flowing through the MOS transistor, thus greatly increasing signal delay time.
Also in the steady state, the voltage applied to the gate-source region of p channel MOS transistor 53 or n channel MOS transistor 54 is 0 V, no current flows through diode 55 or diode 56 as a result, and, therefore, it is difficult to stably set the logic amplitude of the output signal at Vdd-2.multidot.Vbe.
FIG. 26 is a diagram showing a circuit structure for improving the low voltage speed performance of a conventional BiCMOS gate circuit. The circuit structure shown in FIG. 26 is presented by HIRAKI et al., in Proceedings 1990 Spring National Conference of institute of Electronics, Information, Communications and Electrics Engineers of Japan, p. 5-189. The BiCMOS gate circuit shown in FIG. 26 includes a p channel MOS transistor having its one conduction terminal (source) connected to the first power supply potential Vdd, its gate connected to an input signal line 11, and its other conduction terminal (drain) connected to a node N31; a diode 63 connected in the forward direction between nodes N31 and N33; an n channel MOS transistor 62 having its one conduction terminal (drain) connected to node N33, its other conduction terminal (source) connected to a reference potential Vr, and its gate connected to input signal line 11; a resistor 64 connected between node N33 and output signal line 12; and an npn bipolar transistor 65 having its collector connected to the first power supply potential Vdd, its emitter connected to output signal line 12, and its base connected to node N31. The forward voltage Vf of diode 63 is set to be a value smaller than the base-emitter voltage Vbe of bipolar transistor 65 (about 0.5 V). The reference voltage Vr is set to be the value which satisfies the relation represented by Vr=Vf and Vdd=Vh+2.multidot.Vr provided that the logic amplitude of an input signal potential Vin is Vh.
The BiCMOS gate circuit shown in FIG. 26 further includes an n channel MOS transistor 66 having its one conduction terminal (drain) connected to output signal line 12, its gate connected to input signal line, and its other conduction terminal (source) connected to the reference potential Vr through resistor 67, and an npn bipolar transistor 68 having its collector connected to output signal line 12, its base connected to node N32, and its emitter connected to the second power supply potential Vss. The second power supply potential Vss is usually selected to be ground potential VGND. The operation will be briefly described in the following.
With the input signal potential Vin being high, n channel MOS transistors 62 and 66 conduct, whereby bipolar transistor 65 has its base charges extracted and attains the non-conduction state. Bipolar transistor 68 is supplied with base current from signal line 12 through MOS transistor 66 and conducts, thus lowering the potential of output signal line 12 at a high speed. The base potential of bipolar transistor 68 is biased by the reference potential Vr. The potential of output signal line 12 is therefore ultimately pulled down to the level of Vss+Vbe.
With the input signal potential Vin being low, p channel MOS transistor 61 conducts while n channel MOS transistors 62 and 66 are turned off. In this case, npn bipolar transistor 65 conducts, bipolar transistor 68 is turned off, and output signal line 12 is charged through this npn bipolar transistor 65. The charge potential of output signal line 12 finally reaches the level of Vdd-Vbe.
In the case of the circuit structure shown in FIG. 26, in addition to the power supply voltages Vdd and Vss, a certain reference potential Vr should be supplied externally. In this case, the reference potential Vr can be supplied using a diode-connected MOS transistor, but this approach increases the number of elements for forming the circuit.
The BiCMOS logic circuit is usually used with a logic circuit structured exclusively of CMOS transistor circuitry. In this case, the logic circuit formed exclusively of CMOS transistors is provided at the next stage of the BiCMOS logic circuit. However, in the case of the circuit structure shown in FIG. 26, no approach is provided for reducing the logic amplitude in the CMOS logic circuit provided in the next stage. More specifically, the prior art document simply discloses the step of increasing the first power supply potential Vdd of BiCMOS gate circuit to the level of Vcc+2.multidot.Vf when the logic amplitudes of the input signal Vin and the output signal potential Vout are both at the level of Vcc (power supply potential for the operation of the logic circuit), and with the reference potential Vr being set to be approximately identical to the forward voltage Vf of the diode. In this case, in addition to the reference potential Vr, another power supply potential will be necessary as a power supply potential for the operation of the BiCMOS gate circuit.